Vodafone Group network architecture director Santiago Tenorio told Mobile World Live (MWL) a newly-opened chip design R&D centre in Spain would boost its open RAN ambitions while developing related templates available to a broad range of silicon manufacturers.
The centre in Spain opened yesterday (31 January), with 50 of the 700 research staff in a broader digital skills hub focused solely on open RAN.
Tenorio explained open RAN “requires the operator to go deeper into the components and understand the merits and downsides of the different silicon architectures and chips themselves”.
Researchers will focus on influencing “the design and evolution of chips” for all players, the executive told MWL.
The team will first identify architecture and design options before moving to simulation and early benchmark testing. Tenorio said this work will precede development of a public specification which chip manufacturers could access.
Other likely focus areas include advancing Arm and RISC-V architectures; developing 3nm production techniques for RAN silicon; and identifying best practices for hardware acceleration.
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